1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a three-dimensional (3D) semiconductor apparatus.
2. Related Art
In order to meet high integration demands for semiconductor devices, a 3D semiconductor apparatus including a plurality of chips stacked and packaged inside a single package has been developed. Since the 3D semiconductor apparatus includes two or more chips stacked in a vertical direction, the higher integration levels may be provided without utilizing additional space.
A variety of methods may be applied to implement the 3D semiconductor apparatus. One of the methods is to stack a plurality of chips having the same structure and connect the stacked chips through a metallic wire such that the stacked chips operate as one semiconductor apparatus.
In particular, a chip stack method to form one semiconductor memory apparatus by stacking a plurality of semiconductor chips uses a through-chip via to transfer a signal in common to the plurality of semiconductor chips. In general, since a semiconductor chip is fabricated using a silicon wafer, the through-chip via may be referred to as a through-silicon via (TSV).
In general, a semiconductor apparatus using the TSV may include a master chip and a plurality of slave chips which are electrically connected to the master chip through the TSV. In the case of a memory apparatus, the master chip includes all logic circuits in a peripheral circuit area for the operation of the memory apparatus, and the slave chips include a memory core to store data and circuits for a core operation, thereby operating as one semiconductor apparatus.
Although the 3D semiconductor apparatus includes a plurality of chips stacked therein, the plurality of chips share a data input/output line, in order to operate as a single semiconductor apparatus. In a semiconductor apparatus using wire connection, data outputted from a plurality of chips stacked therein may be transferred to a controller through one input/output line. In a semiconductor apparatus using a TSV, data of slave chips may be transferred to a master chip, and then outputted to the outside through a pad provided in the master chip. However, the semiconductor apparatus using a TSV has different signal transfer times and different driving abilities throughout the device, depending on the diameter and length of the TSV, thereby causing different performance levels among the individual chips. Therefore, it is necessary to measure a signal transfer time through the TSV.
FIG. 1 is a diagram schematically illustrating the configuration of a conventional 3D semiconductor apparatus 10.
Referring to FIG. 1, the 3D semiconductor apparatus 10 includes a plurality of chips 11 to 13, a plurality of TSVs 14 to 17 formed through the respective chips 11 to 13, a plurality of connection pads BP1 and BP2 provided between the respective TSVs 14 to 17 and electrically connecting the corresponding TSVs, a plurality of external connection terminals BALL1 and BALL2 to electrically connect the plurality of chips 11 to 13 to a substrate 20, and the substrate 20 electrically connected to the plurality of chips 11 to 13.
A TSV time delay measuring method of the conventional 3D semiconductor apparatus 10 is performed as follows: a total time delay is measured from where an input signal IN is transmitted to a specific external connection terminal to where the input signal IN is outputted to another external connection terminal, and is then divided by the number of TSVs 14 to 17 inside the 3D semiconductor apparatus 10, in order to calculate the time delay of each TSV.
However, the TSV time delay measuring method of the conventional 3D semiconductor apparatus 10 may not be accurate, since there is additional delay caused by the connection pads BP1 and BP2 or PVT (process, voltage, temperature) variation occurring in each chip while the input signal IN is transmitted.